Hi Partners,
Kindly let me know if you have any consultant for the following requirements.
Please respond back with an updated resume and all inclusive rates to recruiter@burgeonits.com
Position: Low Power ASIC Physical Designer
Location: Hillsboro (OR).
Duration: 6 months
Job Description
At least 4 years of experience in the following skills - Netlist-GDS flow with Synthesis, Layout (Floorplan, Place and Route, clock tree synthesis), Static Timing Analysis, Formal Verification, Physical Verification(DRC, LVS) and Power Analysis(IR drop, EMIG), Leakage Power Optimization using ICCLR/PTLR flows, on 22nm, 14nm, or lower process technology
Desired Tools Experience: Synopsys ICC flow, Prime Time, Design Compiler, Redhawk, LEC/Formailty, and Caliber.
At least 4 years of experience in Project life cycle activities on development and maintenance projects.
At least 4 years of experience in Physical Design and STA review.
At least 4 years of experience in ASIC development life cycle.
Ability to work in team in diverse/ multiple stakeholder environment
Thanks & Regards
Raja
Burgeon IT Services LLC.
619 New York Avenue, Claymont, DE 19703
Phone No. : 302-338-9683; 302-220-4724, Fax : 302-355-1559
Email Id : recruiter@burgeonits.com Website: www.burgeonits.com
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